CXL (Compute Express Link) is becoming one of the most important technologies in the evolution of server memory. As AI workloads, databases, virtualization, and high-performance computing demand more memory, traditional server architectures are running into an increasingly expensive problem: how do you provide enough RAM without wasting large amounts of it?
CXL offers a possible solution by allowing processors to connect to memory devices beyond the traditional DIMM slots inside a server.
But CXL is often described as something more ambitious than it actually is today. Can CXL really allow multiple servers to share the same pool of RAM? Can it make memory more flexible and efficient? And could it eventually change the way data centers buy and deploy DRAM?
The short answer is: CXL can already expand server memory, while true large-scale memory pooling and sharing are still evolving.
CXL, or Compute Express Link, is a high-speed interconnect designed to connect CPUs and other compute devices to memory and accelerators.
Traditional server memory is tightly tied to the CPU and motherboard. If a server has 1 TB of DDR5 memory installed, that memory is physically attached to that server. If another server needs more memory, it generally cannot simply borrow unused RAM from the first machine.
CXL changes this architecture.
A CXL-enabled CPU can communicate with external memory devices through the PCIe-based CXL interconnect. This creates the possibility of adding memory capacity without placing all of it directly on the CPU's memory channels.
That sounds simple, but the implications are much larger.
Instead of thinking about memory as something permanently attached to an individual server, data centers can begin treating memory as a resource that can potentially be expanded, pooled, and dynamically allocated.
The most practical CXL application today is memory expansion.
A server may have a certain amount of local DDR5 memory, but some applications require more capacity. Rather than replacing the entire server or installing extremely expensive high-capacity DIMMs, a CXL memory device can provide additional capacity.
The trade-off is latency.
Local DDR5 memory is the fastest option because it is directly connected to the CPU's memory controller. CXL-attached memory introduces additional communication overhead.
In the examples discussed in the full article, local DDR5 access can be around 115 ns, while direct CXL memory can be roughly 230–300 ns. CXL memory accessed through a switch can be slower still, at approximately 490–600 ns.